基于R501双核程序的SCT文件配置分享
以CPU0工程为例，大致介绍SCT文件的几个配置要点。
1.Flash Configuration
R501，程序访问FLASH有两套接口，分别是ITCM和BusMatrix，用户需要根据自身需求进行选择。具体选择路径需要打开工程配置下的debug->flash_download界面下选取
2.RAM Configuration
G32R501有128KB的RAM空间，分为CPU0_ITCM、CPU1_ITCM、CPU0_DTCM、CPU1_DTCM、SRAM1、SRAM2、SRAM3共7个区间。具体的长度分配，用户需要先确定该芯片当前状态下的静态存储分配参数才可确定。
3.Stack / Heap Configuration
重点就是长度的确定，当用户存在数据调用异常时，有可能就存在数据堆栈长度不够的情况。
4.CPU1工程的Flash空间分配
注意双核内存分配不可冲突，不可相互共享！！！
/*--------------------- Flash Configuration ----------------------------------
; <h> Flash Configuration
; <o0> Flash Base Address <0x0-0xFFFFFFFF:8>
; <o1> Flash Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __ROM_BASE 0x00100000 //ITCM路径下的FLASH起始地址
#define __ROM_SIZE 0x00040000
;#define __ROM_BASE 0x08000000 //BusMatrix路径下的FLASH起始地址
;#define __ROM_SIZE 0x00080000
/*--------------------- RAM Configuration ---------------------------
; <h> RAM Configuration
; <o0> RAM Base Address <0x0-0xFFFFFFFF:8>
; <o1> RAM Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
;#define __RAM_BASE 0x20100000
;#define __RAM_SIZE 0x00019000
#define __RAM1_BASE 0x20100000 //SRAM1 16K
#define __RAM1_SIZE 0x00004000
#define __RAM2_BASE 0x20200000 //SRAM2 16K
#define __RAM2_SIZE 0x00004000
#define __RAM3_BASE 0x20300000 //SRAM3 32K
#define __RAM3_SIZE 0x00007000
#define __ITCM_BASE 0x00000000 //ITCM 16K
#define __ITCM_SIZE 0x00004000
#define __DTCM_BASE 0x20000000 //DTCM 16K
#define __DTCM_SIZE 0x00004000
/*--------------------- Stack / Heap Configuration ---------------------------
; <h> Stack / Heap Configuration
; <o0> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; <o1> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
*----------------------------------------------------------------------------*/
#define __STACK_SIZE 0x00001300
#define __HEAP_SIZE 0x00001300
#define __STACK_TOP_LOCATION 3
#if __STACK_TOP_LOCATION == 0
#define __STACK_TOP (__DTCM_BASE + __DTCM_SIZE) /* Default: starts at end of DTCM0 */
#elif __STACK_TOP_LOCATION == 1
#define __STACK_TOP (__RAM1_BASE + __RAM1_SIZE) /* starts at end of SRAM1 */
#elif __STACK_TOP_LOCATION == 2
#define __STACK_TOP (__RAM2_BASE + __RAM2_SIZE) /* starts at end of SRAM2 */
#elif __STACK_TOP_LOCATION == 3
#define __STACK_TOP (__RAM3_BASE + __RAM3_SIZE) /* starts at end of SRAM3 */
#else
#error "Invalid STACK_TOP_LOCATION!"
#endif
#define __HEAP_BASE (AlignExpr((__STACK_TOP - __STACK_SIZE - __HEAP_SIZE), 8))
#define __RO_BASE __ROM_BASE
#define __RO_SIZE __ROM_SIZE
#define __RW1_BASE __RAM1_BASE
#define __RW1_SIZE __RAM1_SIZE
#define __RW2_BASE __RAM2_BASE
#define __RW2_SIZE __RAM2_SIZE
#define __RW3_BASE __RAM3_BASE
#define __RW3_SIZE (__RAM3_SIZE- __STACK_SIZE - __HEAP_SIZE)
#define __RW4_BASE __ITCM_BASE
#define __RW4_SIZE __ITCM_SIZE
#define __RW5_BASE __DTCM_BASE
#define __RW5_SIZE (__DTCM_SIZE)
LR_ROM __RO_BASE __RO_SIZE { ; load region size_region
ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_RAM1 __RW1_BASE __RW1_SIZE { ; SRAM1 data
.ANY (+RW +ZI)
}
RW_RAM2 __RW2_BASE __RW2_SIZE { ; SRAM2 data
.ANY (+RW +ZI)
}
RW_RAM3 __RW3_BASE __RW3_SIZE { ; SRAM3 data
.ANY (+RW +ZI)
; *E501_IQmath_V1.0.1.lib*(+RW +ZI)
}
RW_ITCM __RW4_BASE __RW4_SIZE { ; ITCM data
.ANY (+RW +ZI)
.ANY (itcm.ramfunc)
.ANY (itcm.instruction)
}
RW_DTCM __RW5_BASE __RW5_SIZE { ; DTCM data
.ANY (dtcm0_data)
.ANY (dtcm.smoothtab)
.ANY (+RW +ZI)
}
#if __HEAP_SIZE > 0
ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap
}
#endif
ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack
}
}
#define __ROM1_BASE 0x00140000
#define __ROM1_SIZE 0x00020000
LR_ROM_CPU1 __ROM1_BASE __ROM1_SIZE{
ER_ROM_CPU1 __ROM1_BASE __ROM1_SIZE{
.ANY (cpu1_code)
}
}
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